In an integrated circuit (IC) package assembly, a semiconductor die (also referred to as an integrated circuit (IC) chip or “chip”) may be bonded directly to a package substrate. Such die is formed with interconnects (e.g., solder balls) affixed to its input/output (I/O) bonding pads. During conventional packaging assembly, the die is “flipped” onto its front surface (e.g., active circuit surface) so that the solder bumps form electrical and mechanical connections directly between the die and conductive metal pads on the package substrate.
One concern is that when such an IC package is soldered or otherwise electrically connected to a printed circuit board (PCB), the IC package is subjected to different temperatures during the assembly process. As a result, stresses are built up among package materials (e.g., die, package substrate, bonding materials, etc.) having different coefficients of thermal expansion (CTE) as each package material tends to expand and contract differently.
The CTE difference in die, substrate, and bonding materials may cause the package to warp or bow (e.g., in a concave shape or a convex shape) during temperature excursion, and this warping or bowing may adversely affect the board level reliability of the package. In some cases, the warping of the package may exceed the co-planarity specification for the IC package. Excessive warpage of the IC package may prevent the mounting of the package substrate to the PCB and is one of many factors that cause low interconnect joint yields.